Searching US Patent Collection...

	PAT. NO.		Title
1	6,381,664		System for multisized bus coupling in a packet-switched computer system
2	6,154,777		System for context-dependent name resolution
3	6,101,565		System for multisized bus coupling in a packet-switched computer system
4	5,987,579		Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system
5	5,987,557		Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU)
6	5,970,505		Linking related data in a document set including a plurality of books written by different groups of authors in a computer network
7	5,930,807		Apparatus and method for fast filtering read and write barrier operations in garbage collection system
8	5,907,485		Method and apparatus for flow control in packet-switched computer system
9	5,905,998		Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system
10	5,893,165		System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO
11	5,893,121		System and method for swapping blocks of tagged stack entries between a tagged stack cache and an untagged main memory storage
12	5,892,957		Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system
13	5,887,134		System and method for preserving message order while employing both programmed I/O and DMA operations
14	5,878,264		Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure
15	5,862,356		Pipelined distributed bus arbitration system
16	5,848,423		Garbage collection system and method for locating root set pointers in method activation records
17	5,737,755		System level mechanism for invalidating data stored in the external cache of a processor in a computer system
18	5,710,891		Pipelined distributed bus arbitration system
19	5,706,463		Cache coherent computer system that minimizes invalidation and copyback operations
20	5,692,197		Method and apparatus for reducing power consumption in a computer network without sacrificing performance
21	5,689,713		Method and apparatus for interrupt communication in a packet-switched computer system
22	5,684,977		Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
23	5,657,472		Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
24	5,655,100		Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
25	5,644,753		Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
26	5,634,068		Packet switched cache coherent multiprocessor system
27	5,581,729		Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system