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| United States Patent | 6,002,613 |
| Cloud , et al. | December 14, 1999 |
A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to the memory circuit and can request that data be output on communication lines for reading therefrom. The memory circuit reduces the time needed to read data stored in the memory by providing a valid output data signal. The valid output data signal indicates that data coupled to the communication lines has stabilized and is therefore valid. Different valid output data signals and trigger circuits for producing the signals are described.
| Inventors: | Cloud; Eugene H. (Boise, ID), Williams; Brett (Eagle, ID), Manning; Troy A. (Boise, ID) |
|---|---|
| Assignee: |
Micron, Technology, Inc.
(Boise,
ID)
|
| Family ID: | 24038634 |
| Appl. No.: | 08/966,762 |
| Filed: | November 10, 1997 |
| Application Number | Filing Date | Patent Number | Issue Date | ||
|---|---|---|---|---|---|
| 512326 | Aug 30, 1995 | 5724288 | |||
| Current U.S. Class: | 365/189.15; 365/189.05; 365/189.11; 365/230.06; 365/233.17 |
| Current CPC Class: | G11C 7/1051 (20130101); G11C 11/4076 (20130101); G11C 7/22 (20130101); G11C 7/1063 (20130101) |
| Current International Class: | G11C 7/00 (20060101); G11C 11/4076 (20060101); G11C 7/22 (20060101); G11C 11/407 (20060101); G11C 007/00 () |
| Field of Search: | ;365/189.01,189.05,189.08,233.5,233 |
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"DRAM 1 Meg.times.4 DRAM 5VEDO Page Mode", Micron Technology, Inc. 1995 DRAM Data Book, pp. 1-1 thru 1-30. . "DRAM 2MEG.times.8DRAM 3.3V, EDO Page Mode", Micron Technology Inc., 1995 DRAM Data Book, 1-63 to 1-76, (1995).. |
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