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| United States Patent | 5,991,843 |
| Porterfield , et al. | November 23, 1999 |
| **Please see images for: ( Certificate of Correction ) ** |
A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.
| Inventors: | Porterfield; A. Kent (New Brighton, MN), LaBerge; Paul A. (Shoreview, MN), Jeddeloh; Joe M. (Minneapolis, MN) |
|---|---|
| Assignee: |
Micron Electronics, Inc.
(Nampa,
ID)
|
| Family ID: | 24915108 |
| Appl. No.: | 09/176,059 |
| Filed: | October 20, 1998 |
| Application Number | Filing Date | Patent Number | Issue Date | ||
|---|---|---|---|---|---|
| 725576 | Oct 3, 1996 | 5878235 | |||
| Current U.S. Class: | 710/112; 710/107 |
| Current CPC Class: | G06F 13/36 (20130101); G06F 13/405 (20130101); G06F 13/4027 (20130101) |
| Current International Class: | G06F 13/40 (20060101); G06F 13/36 (20060101); G06F 013/36 () |
| Field of Search: | ;710/112,102,107,129 |
| 4636947 | January 1987 | Ward |
| 5193188 | March 1993 | Franaszek et al. |
| 5327570 | July 1994 | Foster et al. |
| 5485586 | January 1996 | Brash et al. |
| 5615343 | March 1997 | Sarangdhar et al. |
| 5625778 | April 1997 | Childers et al. |
| 5682509 | October 1997 | Kabenjian |
| 5887139 | March 1999 | Hagersten et al. |
Shanley and Anderson, PCI System Architecture, 3d ed., Addison-Wesley Publishing Company, Reading, MA, 1995, Chap. 8, "The Read and Write Transfers," pp. 129-161. . Shanley and Anderson, ISA System Architecture, 3d ed., Addison-Wesley Publishing Company, Reading, MA, 1995, Chap. 16, "ISA Bus Structure," pp. 335-350; Chap. 17, "Types of ISA Bus Cycles," pp. 351-364.. |
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